Xilinx V2.1 Instrukcja Użytkownika Pobierz pdf (Strona 122)

122 Xilinx Development System

Xilinx System Generator v2.1 Reference Guide

The number of bits used to implement a registered mealy state machine is given by

the equations:

where

N = total number of block RAM bits

k =

s = number of states

i = number of input bits

o = number of output bits

The following table gives examples of Block RAM sizes necessary for various state

machines:

The block RAM width and depth limitations are described in the online help for the

Single Port RAM block.

Xilinx LogiCORE

This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE.

The Core datasheet for the Single Port Block Memory may be found locally at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do

c\sp_block_mem.pdf

Number of States Number of

Input Bits

Number of

Output Bits

Block RAM Bits

Needed

2 5 10 704

41232

8 6 7 5120

16 5 4 4096

32 4 3 4096

52 1 11 2176

100 4 5 24576

depth 2

()2

() 2

ki+

width k o+=

N depth width× ko+()2

ki+

()==

log

1 2 ... 117 118 119 120 121 122 123 124 125 126 127 ... 147 148

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Xilinx V2.1 Instrukcja Użytkownika Strona 122