Xilinx ML605 Instrukcja Użytkownika Strona 30
- Strona / 96
- Spis treści
- BOOKMARKI
- ML605 Hardware 1
- User Guide 1
- Revision History 2
- Date Version Revision 3
- Table of Contents 5
- Appendix A: References 6
- Appendix D: ML605 Master UCF 6
- About This Guide 7
- Additional Support Resources 8
- ML605 Evaluation Board 9
- Features 10
- UG534 (v1.8) October 2, 2012 11
- Related Xilinx Documents 12
- Detailed Description 13
- Configuration 15
- I/O Voltage Rails 16
- 2. 512 MB DDR3 Memory SODIMM 17
- References 21
- 3. 128 Mb Platform Flash XL 22
- 4. 32 MB Linear BPI Flash 22
- ML605 Flash Boot Options 23
- 6. USB JTAG 28
- 7. Clock Generation 29
- Silkscreened outline 30
- Socket has notch 30
- SMA Connectors (Differential) 31
- GTX SMA Clock 32
- 10. SFP Module Connector 37
- UG534_13_111709 39
- 12. USB-to-UART Bridge 41
- 13. USB Controller 42
- 14. DVI Codec 43
- 15. IIC Bus 44
- FPGA IIC 45
- INTERFACE 45
- 8 Kb NV Memory 46
- 16. Status LEDs 47
- Ethernet PHY Status LEDs 48
- 17. User I/O 49
- User LEDs 50
- User Pushbutton Switches 51
- User DIP Switch 52
- User SMA GPIO 53
- UG534_22_073109 54
- 18. Switches 55
- SDMX-4-X 57
- JTAG 101 1 Input (TCK) 58
- 21. Power Management 67
- Onboard Power Regulation 68
- 22. System Monitor 71
- System Monitor Header (J35) 72
- 12V Supply Monitor 73
- Fan Controller 74
- 6vlx240tff1156 75
- Configuration Options 76
- Appendix A: References 78
- Additional documentation: 78
- (MT4JSF6464HY-1G1) 78
- W25Q64VSFIG) 78
- Appendix B 79
- Connector Pinout 81
- ML605 Master UCF 83
- Appendix D: ML605 Master UCF 84
- Regulatory and Compliance 95
- Information 95
- Markings 96
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