Xilinx UG492 Instrukcja Użytkownika Pobierz pdf (Strona 139)

Ethernet AVB Endpoint User Guide www.xilinx.com 139

UG492 July 23, 2010

Generating the Core

This section provides detailed instructions for generating the Ethernet AVB Endpoint

example design core.

To generate the core:

1. Start the CORE Generator™ tool.

For general help with starting and using CORE Generator software on your system,

see the documentation supplied with the ISE software, including the CORE Generator

Guide. These documents can be downloaded from:

ww.xilinx.com/support/software_manuals.htm

2. Create a new project.

3. For project options, select the following:

♦ A Virtex®-6, Virtex-5, Spartan®-3, Spartan-3E, Spartan-3A/3A DSP or Spartan-6

device to generate the default Ethernet AVB Endpoint core.

♦ In the Design Entry section, select VHDL or Verilog; then select Other for Vendor.

4. Locate the Ethernet AVB Endpoint core in the taxonomy tree, listed under one of the

following:

♦ Automotive & Industrial/Automotive

♦ Communications & Networking/Ethernet

♦ Communications & Networking/Networking

♦ Communications & Networking/Telecommunications

5. Double-click the core name. A message may appear to indicate the limitations of the

Simulation Only Evaluation license.

6. Click OK; the core customization screen appears.

1 2 ... 134 135 136 137 138 139 140 141 142 143 144 ... 171 172

Brak uwag

Xilinx UG492 Instrukcja Użytkownika Strona 139