Xilinx ML510 Instrukcja Użytkownika

ML510 QuickStartAugust 2008

Hardware Setup• The ML510 uses a DVI videointerface• Connect a DVI monitoror• Use a DVI/VGA adapter to connect a VGA monitor– http://www.belkin.comNot

Hardware Setup• USB Keyboard– www.dell.comNote: Presentation applies to the ML510

Software Setup• Start a Terminal Program for each UART:Note: Presentation applies to the ML510

Factory CompactFlash• The CompactFlash shipped with the ML510 board has the following ace files preloaded:Note: Presentation applies to the ML510

Network Setup• Set PHY0 Jumpers• MII – Connect pins 1 & 2 on J50 and J28 • RGMII – Connect pins 1 & 2 on J50; connect J49Note: Refer to the ML

CompactFlash Setup• Insert the CompactFlash provided with the ML510 fully into the CompactFlash slot on the ML510 board

Equipment Setup• Set SW3 DIP Switches to 00010101 (1 = ON)• Power-up the ML510 boardNote: Presentation applies to the ML510

ACE–Loader• The terminal window also reflects the ACE-loader application• Type the desired number in the terminal window to choose an application • Af

CF1 – TestApp Peripheral• Type 1, to launch the TestApp Peripheral DIMM0 design– Set jumpers for MII; takes several minutes to completeNote: MicroBlaz

CF2 – VxWorks DIMM0• Type 2, to launch the VxWorks on the Pcore DIMM0 designNote: PPC440 DIMM0 Design

Overview• Setup• Boot with ACE-loader ACE File• Observe LCD and Terminal messages • Load new Configuration• Re-load ACE-loader

CF3 – TestApp Peripheral• Type 3, to launch the TestApp Peripheral DIMM1 design– View on COM2; takes several minutes to completeNote: MicroBlaze DIMM1

CF4 – VxWorks DIMM1• Type 4, to launch the VxWorks on the BSB DIMM1 designNote: PPC440 DIMM1 Design

CF5 – Dual VxWorks• Type 5, to launch the Dual Processor VxWorks design– Set jumpers for RGMIINote: Dual PPC440 Design

CF6 – My ACE• Type 6, to launch the placeholder design, my_ace– Same message appears on the MonitorNote: PPC440 Pcore DIMM0 Design

CF7 – Slideshow• Type 7, to launch the slideshow application• The slideshow loads the presentation into memory then presents itNote: Presentation appl

Slideshow• The slideshow app will present a series of slides on the Monitor:Note: Presentation applies to the ML510

Documentation• Virtex-5– Silicon Deviceshttp://www.xilinx.com/products/silicon_solutions– Virtex-5 Multi-Platform FPGAhttp://www.xilinx.com/products/s

Documentation• Virtex-5 – Virtex-5 FPGA User Guidehttp://www.xilinx.com/support/documentation/user_guides/ug190.pdf– Virtex-5 FPGA Configuration User

Documentation• Virtex-5 RocketIO– RocketIO GTP Transceivershttp://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/RocketIO

Documentation• Design Resources– ISE Development Tools and IPhttp://www.xilinx.com/ise– Integrated Software Environment (ISE) Foundation Resourceshttp

ML510 BSB DIMM0 Hardware• The ML510 MicroBlaze design hardware includes:– DDR2 Interface (512 MB)– BRAM – External Memory Controller (EMC)– Networking

Documentation• Additional Design Resources– Customer Supporthttp://www.xilinx.com/support– Xilinx Design Services: http://www.xilinx.com/xds– Titanium

Documentation• Platform Studio– Embedded Development Kit (EDK) Resourceshttp://www.xilinx.com/edk– Embedded System Tools Reference Manualhttp://www.xi

Documentation• PowerPC 440– PowerPC 440 Processorhttp://www.xilinx.com/powerpc– Embedded Processor Block in Virtex-5 FPGAs Reference Guide – UG200http

Documentation• MicroBlaze– MicroBlaze Processorhttp://www.xilinx.com/microblaze– MicroBlaze Processor Reference Guide – UG081http://www.xilinx.com/sup

Documentation• Memory Solutions– Demos on Demand – Memory Interface Solutions with Xilinx FPGAs http://www.demosondemand.com/clients/xilinx/001/page_n

Documentation• ChipScope Pro– ChipScope Pro 10.1i Serial IO Toolkit User Manualhttp://www.xilinx.com/ise/verification/chipscope_pro_siotk_10_1_ug213.p

Documentation• Ethernet– Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper Data Sheethttp://www.xilinx.com/support/documentation/ip_documentation/v5_ema

Documentation• PLB v4.6 IP– Processor Local Bus (PLB) v4.6 Data Sheet – DS531http://www.xilinx.com/support/documentation/ip_documentation/plb_v46.pdf–

Documentation• PLB v4.6 IP– XPS IIC Bus Interface – DS606http://www.xilinx.com/support/documentation/ip_documentation/xps_iic.pdf– XPS SYSACE (System

Documentation• PLB v4.6 IP– XPS General Purpose Input/Output (GPIO) – DS569http://www.xilinx.com/support/documentation/ip_documentation/xps_gpio.pdf–

ML510 BSB DIMM0 Hardware• The ML510 PPC440 design hardware includes:– DDR2 Interface (512 MB)– BRAM – External Memory Controller (EMC)– Networking – U

Documentation• IP– Local Memory Bus Data Sheet – DS445http://www.xilinx.com/support/documentation/ip_documentation/lmb_v10.pdf– Block RAM Block Data S

Documentation• IP– JTAGPPC Controller Data Sheet – DS298http://www.xilinx.com/support/documentation/ip_documentation/jtagppc_cntlr.pdf– Processor Syst

Documentation• ML510– ML510 Overviewhttp://www.xilinx.com/ml510– ML510 Evaluation Platform User Guide – UG356http://www.xilinx.com/support/documentati

Documentation• ML510– ML510 Schematicshttp://www.xilinx.com/support/documentation/boards_and_kits/ml510_schematics.pdf– ML510 Bill of Materialhttp://w

ML510 BSB DIMM1 Hardware• The ML510 MicroBlaze design hardware includes:– DDR2 Interface (512 MB)– BRAM – Networking – UART– Interrupt Controller– Tim

ML510 BSB DIMM1 Hardware• The ML510 PPC440 design hardware includes:– DDR2 Interface (512 MB)– BRAM – External Memory Controller (EMC)– Networking – U

ML510 Dual Processor Hardware• The ML510 Dual Processor design hardware includes:• PPC440_0:– DDR2 Interface (512 MB)– BRAM (64 KB)– External Memory C

Additional Setup Details• Refer to ml510_overview_setup.ppt for details on:– Software Requirements– ML510 Board Setup• Equipment and Cables• Software•

Hardware Setup• Connect the Xilinx Parallel Cable IV (PC4) to the ML510 board• Connect the RS232 nullmodem cable to the ML510 boardNote: Presentation